Tools
Lab #6
Description:
Supporting file for a lab assignment on RISC processor design. This code makes the following assumptions about the Beta design: after reset, the Beta starts executing at location 0; illegal instructions cause a trap to location 4; interrupts cause a trap to location 8.
Resource Type:
Laboratory Assignments
file
11 kB
Lab #6
Course Info
Instructor
Departments
As Taught In
Spring
2009
Level
Course Info
Instructor
Departments
As Taught In
Spring
2009
Level
Learning Resource Types
grading
Exam Solutions
grading
Exams
notes
Lecture Notes
assignment_turned_in
Problem Set Solutions
assignment
Problem Sets
